[verilog] Stoplight

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  1. `timescale 1ns / 1ps
  2. `default_nettype none 
  3. module tlc_fsm(
  4.     output reg [2:0] state, //output for debugging
  5.     output reg RstCount, //always block
  6.     /*another always block four output*/
  7.     output reg [1:0] highwaysignal, farmsignal,
  8.     input wire [31-1:0] count,
  9.     input wire Clk, Rst
  10.     );
  11.     //describe the different states
  12.     parameter S0 = 3'b000,
  13.               S1 = 3'b001,
  14.               S2 = 3'b010,
  15.               S3 = 3'b011,
  16.               S4 = 3'b100,
  17.               S5 = 3'b101;
  18.     //next state
  19.     reg [2:0] next;
  20.     always@(*)
  21.     begin
  22.         if(Rst)
  23.             state <= S0;
  24.         else
  25.             state <= next;
  26.     end
  27.     
  28.     always@(*)
  29.     case(state)
  30.         S0: begin
  31.         highwaysignal = 2'b00;
  32.         farmsignal = 2'b00;
  33.         end
  34.         S1: begin
  35.         highwaysignal = 2'b10;
  36.         farmsignal = 2'b00;
  37.         end
  38.         S2: begin
  39.         highwaysignal = 2'b01;
  40.         farmsignal = 2'b00;
  41.         end
  42.         S3: begin
  43.         highwaysignal = 2'b00;
  44.         farmsignal = 2'b00;
  45.         end
  46.         S4: begin
  47.         highwaysignal = 2'b00;
  48.         farmsignal = 2'b10;
  49.         end
  50.         S5: begin 
  51.         highwaysignal = 2'b00;
  52.         farmsignal = 2'b01;
  53.         end
  54.     endcase
  55.     
  56.     always@(*)
  57.         case(state)
  58.         S0:begin
  59.             if(count == 50000000)
  60.                 RstCount <= 1'b1;
  61.                 next <= S1;
  62.              else
  63.                 next <= S0;
  64.             end
  65.         S1: begin
  66.             if(count == 1500000000)
  67.                 RstCount <= 1'b1;
  68.                 next <= S2;
  69.             else 
  70.                 next <= S1;
  71.             end
  72.         S2: begin
  73.             if(count == 150000000)
  74.                 RstCount <= 1'b1;
  75.                 next <= S3;
  76.             else 
  77.                 next <= S2;
  78.             end
  79.         S3: begin
  80.             if(count == 50000000)
  81.                 RstCount <= 1'b1;
  82.                 next <= S4;
  83.             else
  84.                 next <= S3;
  85.             end
  86.         S4: begin
  87.             if(count == 750000000)
  88.                 RstCount <= 1'b1;
  89.                 Next <= S5;
  90.             else 
  91.                 next <= S4;
  92.             end
  93.         S5: begin
  94.             if(count == 150000000)
  95.                 next <= S0;
  96.                 RstCount <= 1'b1
  97.             else 
  98.                 next <= S5;
  99.             end
  100.         endcase
  101.             
  102.     
  103. endmodule
  104.  

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  • Stoplight
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  • 29 Nov-2022
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