[verilog] Stoplight
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- `timescale 1ns / 1ps
- `default_nettype none
- module tlc_fsm(
- output reg [2:0] state, //output for debugging
- output reg RstCount, //always block
- /*another always block four output*/
- output reg [1:0] highwaysignal, farmsignal,
- input wire [31-1:0] count,
- input wire Clk, Rst
- );
- //describe the different states
- parameter S0 = 3'b000,
- S1 = 3'b001,
- S2 = 3'b010,
- S3 = 3'b011,
- S4 = 3'b100,
- S5 = 3'b101;
- //next state
- reg [2:0] next;
- always@(*)
- begin
- if(Rst)
- state <= S0;
- else
- state <= next;
- end
- always@(*)
- case(state)
- S0: begin
- highwaysignal = 2'b00;
- farmsignal = 2'b00;
- end
- S1: begin
- highwaysignal = 2'b10;
- farmsignal = 2'b00;
- end
- S2: begin
- highwaysignal = 2'b01;
- farmsignal = 2'b00;
- end
- S3: begin
- highwaysignal = 2'b00;
- farmsignal = 2'b00;
- end
- S4: begin
- highwaysignal = 2'b00;
- farmsignal = 2'b10;
- end
- S5: begin
- highwaysignal = 2'b00;
- farmsignal = 2'b01;
- end
- endcase
- always@(*)
- case(state)
- S0:begin
- if(count == 50000000)
- RstCount <= 1'b1;
- next <= S1;
- else
- next <= S0;
- end
- S1: begin
- if(count == 1500000000)
- RstCount <= 1'b1;
- next <= S2;
- else
- next <= S1;
- end
- S2: begin
- if(count == 150000000)
- RstCount <= 1'b1;
- next <= S3;
- else
- next <= S2;
- end
- S3: begin
- if(count == 50000000)
- RstCount <= 1'b1;
- next <= S4;
- else
- next <= S3;
- end
- S4: begin
- if(count == 750000000)
- RstCount <= 1'b1;
- Next <= S5;
- else
- next <= S4;
- end
- S5: begin
- if(count == 150000000)
- next <= S0;
- RstCount <= 1'b1
- else
- next <= S5;
- end
- endcase
- endmodule
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