[verilog] tlc_controller_2.v

Viewer

copydownloadembedprintName: tlc_controller_2.v
  1. `default_nettype none
  2.  
  3. module tlc_controller_ver2(
  4.     output wire [1:0] highwaySignal, farmSignal,            // outputs
  5.     output wire [3:0] JB,
  6.     input wire Clk,                                 // inputs
  7.     input wire Rst,
  8.     input wire sensor
  9.     );
  10.     
  11.     wire RstSync;               // reset synchronizer
  12.     wire RstCount;              // reset count
  13.     reg [30:0] Count;           // count
  14.     
  15.     assign JB[3] = RstCount;
  16.     
  17.     synchronizer syncRst(RstSync, Rst, Clk);        // synchronizer
  18.     
  19.     tlc_fsm_2 FSM(.state(JB[2:0]),              // FSM
  20.     .RstCount(RstCount), 
  21.     .highwaySignal(highwaySignal), 
  22.     .farmSignal(farmSignal), 
  23.     .Count(Count), 
  24.     .Clk(Clk),
  25.     .Rst(Rst),
  26.     .sensor(sensor));
  27.     
  28.     always@(posedge Clk)                // clock
  29.         if (RstCount)
  30.             Count <= 0;
  31.         else
  32.             begin
  33.                Count <= Count + 1;
  34.             end
  35.     
  36. endmodule

Editor

You can edit this paste and save as new:


File Description
  • tlc_controller_2.v
  • Paste Code
  • 02 Dec-2022
  • 968 Bytes
You can Share it: