[verilog] traffic controller pre lab

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copydownloadembedprintName: traffic controller pre lab
  1. `timescale 1ns / 1ps
  2. `default_nettype none
  3. module tlc_fsm(state, RstCount, highwaySignal, farmSignal, Count, Clk, Rst);
  4.     output reg [2:0] state; //output for debugging
  5.     output reg RstCount; //use an always block
  6.     //another always block for these as well
  7.     output reg [1:0] highwaySignal, farmSignal;
  8.     input wire [30:0] Count;
  9.     input wire Clk, Rst; //clock and reset
  10.     
  11.     paramter S0 = 3'b000,
  12.              S1 = 3'b001,
  13.              S2 = 3'b010,
  14.              S3 = 3'b011,
  15.              S4 = 3'b100,
  16.              S5 = 3'b101;
  17.     intermediate nets
  18.     reg [2:0] nextState; //driven in always block
  19.     
  20.     //signals green(11), yellow(10), red(01)
  21.     always@(*)
  22.         case(state)
  23.             S0: begin
  24.                 highwaySignal = 2'b01;
  25.                 farmSignal = 2'b01;
  26.                 if(Count = 31'b10111110101111000010000000) //1 second
  27.                     nextState = S1;
  28.                     RstCount = 1;
  29.                 else
  30.                     nextState = S0;
  31.                     RstCount = 0;
  32.             end
  33.             S1: begin
  34.                 highwaySignal = 2'b11;
  35.                 farmSignal = 2'b01;
  36.                 if(Count == 31'b1011001011010000010111100000000) //30 seconds
  37.                     nextState = S2;
  38.                     RstCount = 1;
  39.                 else
  40.                     nextState = S1;
  41.                     RstCount = 0;
  42.             end
  43.             S2: begin
  44.                 highwaySignal = 2'b10;
  45.                 farmSignal = 2'b01;
  46.                 if(Count = 31'b1000111100001101000110000000) //3 seconds
  47.                     nextState = S3;
  48.                     RstCount = 1;
  49.                 else
  50.                     nextState = S2;
  51.                     RstCount = 0;
  52.             end
  53.             S3: begin
  54.                 highwaySignal = 2'b01;
  55.                 farmSignal = 2'b01;
  56.                 if(Count = 31'b10111110101111000010000000) //1 second
  57.                     nextState = S4;
  58.                     RstCount = 1;
  59.                 else
  60.                     nextState = S3;
  61.                     RstCount = 0;
  62.             end
  63.             S4: begin
  64.                 highwaySignal = 2'b01;
  65.                 farmSignal = 2'b11;
  66.                 if(Count = 31'b101100101101000001011110000000) //15 seconds
  67.                     nextState = S5;
  68.                     RstCount = 1;
  69.                 else
  70.                     nextState = S4;
  71.                     RstCount = 0;
  72.             end
  73.             S5: begin
  74.                 highwaySignal = 2'b01;
  75.                 farmSignal = 2'b10;
  76.                 if(Count = 31'b1000111100001101000110000000) //3 seconds
  77.                     nextState = S0;
  78.                     RstCount = 1;
  79.                 else
  80.                     nextState = S5;
  81.                     RstCount = 0;
  82.             end
  83.         endcase
  84.     always@(posedge Clk)
  85.         if(Rst)
  86.             state <= S0;
  87.         else
  88.             state <= nextState;
  89.     
  90. endmodule

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  • 29 Nov-2022
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