[verilog] traffic controller fsm part 1
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- `timescale 1ns / 1ps
- `default_nettype none
- module tlc_fsm(state, RstCount, highwaySignal, farmSignal, Count, Clk, Rst);
- output reg [2:0] state; //output for debugging
- output reg RstCount; //use an always block
- //another always block for these as well
- output reg [1:0] highwaySignal, farmSignal;
- input wire [30:0] Count;
- input wire Clk, Rst; //clock and reset
- parameter S0 = 3'b000,
- S1 = 3'b001,
- S2 = 3'b010,
- S3 = 3'b011,
- S4 = 3'b100,
- S5 = 3'b101;
- //intermediate nets
- reg [2:0] nextState; //driven in always block
- //signals green(11), yellow(10), red(01)
- always@(*)
- case(state)
- S0: begin
- highwaySignal = 2'b01;
- farmSignal = 2'b01;
- if(Count == 31'b10111110101111000010000000) //1 second or 50,000,000 clock cycles
- begin
- nextState = S1;
- RstCount = 1;
- end
- else
- begin
- nextState = S0;
- RstCount = 0;
- end
- end
- S1: begin
- highwaySignal = 2'b11;
- farmSignal = 2'b01;
- if(Count == 31'b1011001011010000010111100000000) //30 seconds
- begin
- nextState = S2;
- RstCount = 1;
- end
- else
- begin
- nextState = S1;
- RstCount = 0;
- end
- end
- S2: begin
- highwaySignal = 2'b10;
- farmSignal = 2'b01;
- if(Count == 31'b1000111100001101000110000000) //3 seconds
- begin
- nextState = S3;
- RstCount = 1;
- end
- else
- begin
- nextState = S2;
- RstCount = 0;
- end
- end
- S3: begin
- highwaySignal = 2'b01;
- farmSignal = 2'b01;
- if(Count == 31'b10111110101111000010000000) //1 second
- begin
- nextState = S4;
- RstCount = 1;
- end
- else
- begin
- nextState = S3;
- RstCount = 0;
- end
- end
- S4: begin
- highwaySignal = 2'b01;
- farmSignal = 2'b11;
- if(Count == 31'b101100101101000001011110000000) //15 seconds
- begin
- nextState = S5;
- RstCount = 1;
- end
- else
- begin
- nextState = S4;
- RstCount = 0;
- end
- end
- S5: begin
- highwaySignal = 2'b01;
- farmSignal = 2'b10;
- if(Count == 31'b1000111100001101000110000000) //3 seconds
- begin
- nextState = S0;
- RstCount = 1;
- end
- else
- begin
- nextState = S5;
- RstCount = 0;
- end
- end
- endcase
- always@(posedge Clk)
- if(Rst)
- state <= S0;
- else
- state <= nextState;
- endmodule
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