[verilog] traffic controller fsm part 1

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copydownloadembedprintName: traffic controller fsm part 1
  1. `timescale 1ns / 1ps
  2. `default_nettype none
  3. module tlc_fsm(state, RstCount, highwaySignal, farmSignal, Count, Clk, Rst);
  4.     output reg [2:0] state; //output for debugging
  5.     output reg RstCount; //use an always block
  6.     //another always block for these as well
  7.     output reg [1:0] highwaySignal, farmSignal;
  8.     input wire [30:0] Count;
  9.     input wire Clk, Rst; //clock and reset
  10.     
  11.     parameter S0 = 3'b000,
  12.              S1 = 3'b001,
  13.              S2 = 3'b010,
  14.              S3 = 3'b011,
  15.              S4 = 3'b100,
  16.              S5 = 3'b101;
  17.     //intermediate nets
  18.     reg [2:0] nextState; //driven in always block
  19.     
  20.     //signals green(11), yellow(10), red(01)
  21.     always@(*)
  22.         case(state)
  23.             S0: begin
  24.                 highwaySignal = 2'b01;
  25.                 farmSignal = 2'b01;
  26.                 if(Count == 31'b10111110101111000010000000) //1 second or 50,000,000 clock cycles
  27.                     begin
  28.                     nextState = S1;
  29.                     RstCount = 1;
  30.                     end
  31.                 else
  32.                     begin
  33.                     nextState = S0;
  34.                     RstCount = 0;
  35.                     end
  36.             end
  37.             S1: begin
  38.                 highwaySignal = 2'b11;
  39.                 farmSignal = 2'b01;
  40.                 if(Count == 31'b1011001011010000010111100000000) //30 seconds
  41.                     begin
  42.                     nextState = S2;
  43.                     RstCount = 1;
  44.                     end
  45.                 else
  46.                     begin
  47.                     nextState = S1;
  48.                     RstCount = 0;
  49.                     end
  50.             end
  51.             S2: begin
  52.                 highwaySignal = 2'b10;
  53.                 farmSignal = 2'b01;
  54.                 if(Count == 31'b1000111100001101000110000000) //3 seconds
  55.                     begin
  56.                     nextState = S3;
  57.                     RstCount = 1;
  58.                     end
  59.                 else
  60.                     begin
  61.                     nextState = S2;
  62.                     RstCount = 0;
  63.                     end
  64.             end
  65.             S3: begin
  66.                 highwaySignal = 2'b01;
  67.                 farmSignal = 2'b01;
  68.                 if(Count == 31'b10111110101111000010000000) //1 second
  69.                     begin
  70.                     nextState = S4;
  71.                     RstCount = 1;
  72.                     end
  73.                 else
  74.                     begin
  75.                     nextState = S3;
  76.                     RstCount = 0;
  77.                     end
  78.             end
  79.             S4: begin
  80.                 highwaySignal = 2'b01;
  81.                 farmSignal = 2'b11;
  82.                 if(Count == 31'b101100101101000001011110000000) //15 seconds
  83.                     begin
  84.                     nextState = S5;
  85.                     RstCount = 1;
  86.                     end
  87.                 else
  88.                     begin
  89.                     nextState = S4;
  90.                     RstCount = 0;
  91.                     end
  92.             end
  93.             S5: begin
  94.                 highwaySignal = 2'b01;
  95.                 farmSignal = 2'b10;
  96.                 if(Count == 31'b1000111100001101000110000000) //3 seconds
  97.                     begin
  98.                     nextState = S0;
  99.                     RstCount = 1;
  100.                     end
  101.                 else
  102.                     begin
  103.                     nextState = S5;
  104.                     RstCount = 0;
  105.                     end
  106.             end
  107.         endcase
  108.     always@(posedge Clk)
  109.         if(Rst)
  110.             state <= S0;
  111.         else
  112.             state <= nextState;
  113.     
  114. endmodule

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  • 30 Nov-2022
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