[verilog] part 1 controller

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copydownloadembedprintName: part 1 controller
  1. `default_nettype none
  2.  
  3. //this module describes the top level traffic light controller module
  4. module tlc_controller_ver1(highwaySignal, farmSignal, JB, Clk, Rst);
  5.     output wire [1:0] highwaySignal, farmSignal;//connected to LEDs
  6.     //output state for debugging
  7.     output wire [3:0] JB; 
  8.     input wire Clk;
  9.     //the buttons provide input to our top-level circuit
  10.     input wire Rst; //use as reset
  11.     
  12.     //intermediate nets
  13.     wire RstSync;
  14.     wire RstCount;
  15.     reg[30:0] Count;
  16.     
  17.     assign JB[3] = RstCount;
  18.     
  19.     //synchronize button inputs
  20.     synchronizer syncRst(RstSync, Rst, Clk);
  21.     
  22.     //instantiate FSM
  23.     tlc_fsm FSM(
  24.         .state(JB[2:0]), //wire state up to JB for debug
  25.         .RstCount(RstCount),
  26.         .highwaySignal(highwaySignal),
  27.         .farmSignal(farmSignal),
  28.         .Count(Count),
  29.         .Clk(Clk),
  30.         .Rst(RstSync)
  31.     );
  32.     //describe counter with a synchronous reset here
  33.     always@(posedge Clk)
  34.         if(RstCount)
  35.             Count <= 1'b0;
  36.         else
  37.             Count <= Count + 1;
  38.     
  39. endmodule

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  • 30 Nov-2022
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