[verilog] part 1 controller
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- `default_nettype none
- //this module describes the top level traffic light controller module
- module tlc_controller_ver1(highwaySignal, farmSignal, JB, Clk, Rst);
- output wire [1:0] highwaySignal, farmSignal;//connected to LEDs
- //output state for debugging
- output wire [3:0] JB;
- input wire Clk;
- //the buttons provide input to our top-level circuit
- input wire Rst; //use as reset
- //intermediate nets
- wire RstSync;
- wire RstCount;
- reg[30:0] Count;
- assign JB[3] = RstCount;
- //synchronize button inputs
- synchronizer syncRst(RstSync, Rst, Clk);
- //instantiate FSM
- tlc_fsm FSM(
- .state(JB[2:0]), //wire state up to JB for debug
- .RstCount(RstCount),
- .highwaySignal(highwaySignal),
- .farmSignal(farmSignal),
- .Count(Count),
- .Clk(Clk),
- .Rst(RstSync)
- );
- //describe counter with a synchronous reset here
- always@(posedge Clk)
- if(RstCount)
- Count <= 1'b0;
- else
- Count <= Count + 1;
- endmodule
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