[verilog] tlc_controller.v
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- `default_nettype none
- module tlc_controller_ver1(
- output wire [1:0] highwaySignal, farmSignal, // outputs
- output wire [3:0] JB,
- input wire Clk, // inputs
- input wire Rst
- );
- wire RstSync; // reset synchronizer
- wire RstCount; // reset count
- reg [30:0] Count; // counter
- assign JB[3] = RstCount;
- synchronizer syncRst(RstSync, Rst, Clk); // synchronizer
- tlc_fsm FSM(.state(JB[2:0]), // FSM
- .RstCount(RstCount),
- .highwaySignal(highwaySignal),
- .farmSignal(farmSignal),
- .Count(Count),
- .Clk(Clk),
- .Rst(Rst));
- always@(posedge Clk) // clock and counter
- if (RstCount)
- Count <= 0;
- else
- begin
- Count <= Count + 1;
- end
- endmodule
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