[verilog] tlc_controller.v

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  1. `default_nettype none
  2.  
  3. module tlc_controller_ver1(
  4.     output wire [1:0] highwaySignal, farmSignal,            // outputs
  5.     output wire [3:0] JB,
  6.     input wire Clk,                     // inputs
  7.     input wire Rst
  8.     );
  9.     
  10.     wire RstSync;               // reset synchronizer
  11.     wire RstCount;              // reset count
  12.     reg [30:0] Count;           // counter
  13.     
  14.     assign JB[3] = RstCount;
  15.     
  16.     synchronizer syncRst(RstSync, Rst, Clk);        // synchronizer
  17.     
  18.     tlc_fsm FSM(.state(JB[2:0]),                // FSM
  19.     .RstCount(RstCount), 
  20.     .highwaySignal(highwaySignal), 
  21.     .farmSignal(farmSignal), 
  22.     .Count(Count), 
  23.     .Clk(Clk),
  24.     .Rst(Rst));
  25.     
  26.     always@(posedge Clk)            // clock and counter
  27.         if (RstCount)
  28.             Count <= 0;
  29.         else
  30.             begin
  31.                Count <= Count + 1;
  32.             end
  33.     
  34. endmodule

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  • 02 Dec-2022
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