[verilog] tlc_fsm_2.v
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- `default_nettype none
- `define sec1 50000000 // 1 second
- `define sec3 150000000 // 3 seconds
- `define sec15 750000000 // 15 seconds
- `define sec30 1500000000 // 30 seconds
- module tlc_fsm_2(
- output reg [2:0] state, // outputs
- output reg RstCount,
- output reg [1:0] highwaySignal, farmSignal,
- input wire [30:0] Count, // inputs
- input wire Clk, Rst, sensor
- );
- parameter S0 = 3'b000, // states
- S1 = 3'b001,
- S2 = 3'b010,
- S3 = 3'b011,
- S4 = 3'b100,
- S5 = 3'b101;
- parameter red = 2'b00, // red // highway signal output
- green = 2'b01, // green
- yellow = 2'b10; // yellow
- reg [2:0] nextState; // next state
- // output logic
- always@(state or Count)
- case (state)
- S0: begin
- highwaySignal = red;
- farmSignal = red;
- if(Count == `sec1)
- RstCount = 1'b1;
- else
- RstCount = 1'b0;
- end
- S1: begin
- highwaySignal = green;
- farmSignal = red;
- if(Count == `sec30)
- RstCount = 1'b1;
- else
- RstCount = 1'b0;
- end
- S2: begin
- highwaySignal = yellow;
- farmSignal = red;
- if(Count == `sec3)
- RstCount = 1'b1;
- else
- RstCount = 1'b0;
- end
- S3: begin
- highwaySignal = red;
- farmSignal = red;
- if(Count == `sec1)
- RstCount = 1'b1;
- else
- RstCount = 1'b0;
- end
- S4: begin
- highwaySignal = red;
- farmSignal = green;
- if(Count == `sec15)
- RstCount = 1'b1;
- else
- RstCount = 1'b0;
- end
- S5: begin
- highwaySignal = red;
- farmSignal = yellow;
- if(Count == `sec3)
- RstCount = 1'b1;
- else
- RstCount = 1'b0;
- end
- endcase
- // next state logic
- always@(*)
- case(state)
- S0: begin
- if(Count == `sec1)
- nextState <= S1;
- else
- nextState <= S0;
- end
- S1: begin
- if(sensor == 1'b1 && Count == `sec30)
- nextState <= S2;
- else
- nextState <= S1;
- end
- S2: begin
- if(Count == `sec3)
- nextState <= S3;
- else
- nextState <= S2;
- end
- S3: begin
- if(Count == `sec1)
- nextState <= S4;
- else
- nextState <= S3;
- end
- S4: begin
- if((sensor == 1'b0 && Count == `sec3) || Count == `sec15)
- nextState <= S5;
- else
- nextState <= S4;
- end
- S5: begin
- if(Count == `sec3)
- nextState <= S0;
- else
- nextState <= S5;
- end
- endcase
- always@(posedge Clk) // clock circuit
- if(Rst)
- state <= S0;
- else
- state <= nextState;
- endmodule
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