[verilog] tlc_fsm_2.v

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  1. `default_nettype none
  2. `define sec1 50000000           // 1 second
  3. `define sec3 150000000          // 3 seconds
  4. `define sec15 750000000         // 15 seconds
  5. `define sec30 1500000000        // 30 seconds
  6.  
  7.  
  8. module tlc_fsm_2(
  9.     output reg [2:0] state,                         // outputs
  10.     output reg RstCount,
  11.     output reg [1:0] highwaySignal, farmSignal,
  12.     input wire [30:0] Count,                        // inputs
  13.     input wire Clk, Rst, sensor
  14.     );
  15.     
  16.     parameter S0 = 3'b000,          // states
  17.                 S1 = 3'b001,
  18.                 S2 = 3'b010,
  19.                 S3 = 3'b011,
  20.                 S4 = 3'b100,
  21.                 S5 = 3'b101;
  22.                 
  23.     parameter red = 2'b00,    // red      // highway signal output
  24.                 green = 2'b01,    // green
  25.                 yellow = 2'b10;    // yellow
  26.                 
  27.     
  28.     reg [2:0] nextState;            // next state
  29.     
  30.     // output logic
  31.     always@(state or Count)
  32.         case (state)
  33.             S0: begin
  34.                 highwaySignal = red;
  35.                 farmSignal = red; 
  36.                 if(Count == `sec1) 
  37.                     RstCount = 1'b1;
  38.                 else
  39.                     RstCount = 1'b0;
  40.             end
  41.             S1: begin
  42.                 highwaySignal = green;
  43.                 farmSignal = red;
  44.                 if(Count == `sec30) 
  45.                     RstCount = 1'b1;
  46.                 else
  47.                     RstCount = 1'b0;
  48.             end
  49.             S2: begin
  50.                 highwaySignal = yellow;
  51.                 farmSignal = red;
  52.                 if(Count == `sec3) 
  53.                     RstCount = 1'b1;
  54.                 else
  55.                     RstCount = 1'b0;
  56.             end
  57.             S3: begin
  58.                 highwaySignal = red;
  59.                 farmSignal = red;
  60.                 if(Count == `sec1) 
  61.                     RstCount = 1'b1;
  62.                 else
  63.                     RstCount = 1'b0;
  64.             end
  65.             S4: begin
  66.                 highwaySignal = red;
  67.                 farmSignal = green;
  68.                 if(Count == `sec15) 
  69.                     RstCount = 1'b1;
  70.                 else
  71.                     RstCount = 1'b0;
  72.             end
  73.             S5: begin
  74.                 highwaySignal = red;
  75.                 farmSignal = yellow;
  76.                 if(Count == `sec3) 
  77.                     RstCount = 1'b1;
  78.                 else
  79.                     RstCount = 1'b0;
  80.             end
  81.         endcase
  82.                     
  83.     // next state logic
  84.     always@(*)
  85.         case(state)
  86.             S0: begin
  87.                 if(Count == `sec1)
  88.                     nextState <= S1;
  89.                 else
  90.                     nextState <= S0;
  91.             end
  92.             S1: begin
  93.                 if(sensor == 1'b1 && Count == `sec30)
  94.                     nextState <= S2;
  95.                 else
  96.                     nextState <= S1;
  97.             end
  98.             S2: begin
  99.                 if(Count == `sec3)
  100.                     nextState <= S3;
  101.                 else
  102.                     nextState <= S2;
  103.             end
  104.             S3: begin
  105.                 if(Count == `sec1)
  106.                     nextState <= S4;
  107.                 else
  108.                     nextState <= S3;
  109.             end
  110.             S4: begin
  111.                 if((sensor == 1'b0 && Count == `sec3) || Count == `sec15)
  112.                     nextState <= S5;
  113.                 else
  114.                     nextState <= S4;
  115.             end
  116.             S5: begin
  117.                 if(Count == `sec3)
  118.                     nextState <= S0;
  119.                 else
  120.                     nextState <= S5;
  121.             end
  122.         endcase
  123.     
  124.     always@(posedge Clk)            // clock circuit
  125.         if(Rst)
  126.             state <= S0;
  127.         else
  128.             state <= nextState;
  129.     
  130.     
  131. endmodule
  132.  

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  • 02 Dec-2022
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