[verilog] RTL Modeling

Viewer

copydownloadembedprintName: RTL Modeling
  1. module counter(input clk, reset, output reg [3:0] count);
  2.     always @(posedge clk or negedge reset) begin
  3.         if (!reset) count <= 4'b0000;
  4.         else count <= count + 1;
  5.     end
  6. endmodule
  7.  

Editor

You can edit this paste and save as new:


File Description
  • RTL Modeling
  • Paste Code
  • 27 Apr-2024
  • 202 Bytes
You can Share it: